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TDA7346
DIGITAL CONTROLLED SURROUND SOUND MATRIX
1 STEREO INPUT THREE INDEPENDENT SURROUND MODES ARE AVAILABLE MOVIE, MUSIC AND SIMULATED - MUSIC: 4 SELECTABLE RESPONSES - MOVIE AND SIMULATED: 256 SELECTABLE RESPONSES TWO INDEPENDENT INPUT ATTENUATORS IN 0.31dB FOR BALANCE FACILITY ALL FUNCTIONS PROGRAMMABLE VIA SERIAL BUS DESCRIPTION The TDA7346 reproduces surround sound by using phase shifters and a signal matrix. Control of all the functions is accomplished by serial bus. The AC signal setting is obtained by resistor netBLOCK DIAGRAM
SO20
DIP20
ORDERING NUMBER: TDA7346 (DIP20) TDA7346D (SO20)
works and switches combined with operational amplifiers.
5.6nF
680nF
100nF
4.7nF
22nF
22nF
LP1
HP1
HP2
PS1
PS2
PS3
PS4
100nF L-in 100K
RLP1
RHP1 R5 R6 +
RPS1
RPS2
RPS3
RPS4
MIXING AMP
Lout
PS1 90Hz
PS2 4KHz
PS3 400Hz
PS4 400Hz
+
SIM MUSIC MOVIE/ MUSIC PHASE SHIFTER
100nF R-in 100K SUPPLY MIXING AMP Rout
VS
AGND
CREF
February 1997
+
L-R LPF 9KHz C5 22F LP 1.2nF
+
OFF
MOVIE/SIM SCL I2C BUS DECODER LATCHES SDA DIG GND ADDR
EFFECT CONTROL
REAR
D94AU122A
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TDA7346
ABSOLUTE MAXIMUM RATINGS
Symbol VS T amb Tstg Operating Supply Voltage Operating Ambient Temperature Storage Temperature Range Parameter Value 10.5 -40 to 85 -55 to +150 Unit V C C
PIN CONNECTION
PS1 VS CREF L-in LP REAR Lout SDA SCL DIG GND
1 2 3 4 5 6 7 8 9 10
D94AU128
20 19 18 17 16 15 14 13 12 11
PS2 LP1 HP1 HP2 R-in PS3 PS4 Rout ADDR AGND
THERMAL DATA
Symbol R th j-pins Thermal Resistance Junction-pins Description Ma x. Value 85 Unit C/W
QUICK REFERENCE DATA
Symbol VS VCL THD S/N SC Supply Voltage Max. input signal handling Total Harmonic Distortion V = 1Vrms f = 1KHz Signal to Noise Ratio V out = 1Vrms (mode = OFF) Channel Separation f = 1KHz Parameter Min. 7 2 0.02 106 70 0.1 Typ. 9 Max. 10.2 Unit V Vrms % dB dB
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TDA7346
TEST CIRCUIT
REAR HP1 680nF C16 0.1F HP2 L-in VS 2 100nF C2 PS3 22nF C4 PS4 22nF C5 15 20 PS2 4.7nF C13 CREF 22F C3 18 6 Lout 7 SCL 9 SDA 8 5 LP 1.2nF C6 R-in LP1 0.1F
17 16 19
4
C17
C7 5.6nF C15
10F C1
TDA7346
1
PS1 100nF C14
14 13 Rout 11 AGND 10 DIG GND 12 ADDR
3
D93AU040C
ELECTRICAL CHARACTERISTICS (refer to the test circuit Tamb = 25C, VS = 9V, RL = 10K, RG = 600, all controls flat (G = 0),Effect Ctrl = -6dB, MODE = OFF; f = 1KHz unless otherwise specified)
Symbol Parameter Test Condition Min. Typ. Max. Unit
SUPPLY
VS IS SVR Supply Voltage Supply Current Ripple Rejection LCH / RCH out, Mode = OFF 60 7 9 10 80 10.2 V mA dB
INPUT STAGE
R II V CL C RANGE AVMIN AVMAX ASTEP VDC Input Resistance Clipping Level Control Range Min. Attenuation Max. Attenuation Step Resolution DC Steps adjacent att. step -1 THD = 0.3%; Lin or Rin THD = 0.3%; Rin + Lin (2) 2 100 2.5 3.0 20 0 20 0.31 0 1 K Vrms Vrms dB dB dB dB mV
EFFECT CONTROL
C RANGE SSTEP Control Range Step Resolution - 21 1 -6 dB dB
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TDA7346
ELECTRICAL CHARACTERISTICS (continued) SURROUND SOUND MATRIX
Symbol GOFF Parameter In-phase Gain (OFF) Test Condition Mode OFF, Input signal of 1kHz, 1.4 Vp-p, Rin Rout L in Lout Mode OFF, Input signal of 1kHz, 1.4 Vp-p (Rin Rout), (Lin Lout) Movie mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p R in Rout, Lin Lout Movie mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p R in Rout, Lin Lout Movie mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p (Rin Rout) - (Lin Lout) Music mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p (Rin Rout) - (Lin Lout) Music mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p R in Rout, Lin Lout Music mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p (Rin Rout) - (Lin Lout) Simulated Mode, EffectCtrl = -6dB Input signal of 250Hz, 1.4 Vp-p, Rin and Lin Lout Simulated Mode, EffectCtrl = -6dB Input signal of 1kHz, 1.4 Vp-p, Rin and Lin Lout Simulated Mode, EffectCtrl = 6dB Input signal of 3.6kHz, 1.4 Vp-p, Rin and Lin Lout Simulated Mode, EffectCtrl = -6dB Input signal of 250Hz, 1.4 Vp-p, Rin and Lin R out Simulated Mode, EffectCtrl = -6dB Input signal of 1kHz, 1.4 Vp-p, Rin and Lin R out Simulated Mode, EffectCtrl = -6dB Input signal of 3.6kHz, 1.4 Vp-p, Rin and Lin Rout at POR at POR at POR at POR Min. -1.5 Typ. 0 Max. 1.5 Unit dB
DGOFF
LR In-phase Gain Difference (OFF) In-phase Gain (Movie 1) RPS1, RPS2, RPS3, RPS4 = POR Preset In-phase Gain (Movie 2) RPS1, RPS2, RPS3, RPS4 = POR Preset LR In-phase Gain Difference (Movie) In-phase Gain (Music 1) RPS1 = POR PRESET In-phase Gain (Music 2) RPS1 = POR PRESET LR In-phase Gain Difference (Music) Simulated L Output 1 RPS1, RPS2, RPS3, RPS4 = POR Preset Simulated L Output 2 RPS1, RPS2, RPS3, RPS4 = POR Preset Simulated L Output 3 RPS1, RPS2, RPS3, RPS4 = POR Preset Simulated R Output 1 RPS1, RPS2, RPS3, RPS4 = POR Preset Simulated R Output 2 RPS1, RPS2, RPS3, RPS4 = POR Preset Simulated R Output 3 RPS1, RPS2, RPS3, RPS4 = POR Preset Low Pass Filter Resistance Phase Shifter 1 Resistance Phase Shifter 2 Resistance Phase Shifter 3 Resistance Phase Shifter 4 Resistance High Pass Filter Resistance LP Pin Impedance
-1.5
0
1.5
dB
GMOV1
7
dB
GMOV2
8
dB
DGMOV
0
dB
GMUS1
6
dB
GMUS2
7.5
dB
DGMUS
0
dB
LMON1
4.5
dB
LMON2
- 4.0
dB
L MON3
7.0
dB
R MON1
- 4.5
dB
R MON2
3.8
dB
R MON3
- 20
dB
R LP1 RPS1 RPS2 RPS3 RPS2 RHPI RLPF
10 17.95 8.465 18.050 18.050 60 10
K k K K K K K
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TDA7346
ELECTRICAL CHARACTERISTICS (continued)
Symbol Parameter Test Condition Min. Typ. Max. Unit
AUDIO OUTPUTS
VOCL R OUT VOUT Clipping Level Output resistance DC Voltage Level d = 0.3% 2 100 3.5 2.5 200 3.8 300 4.1 Vrms V
GENERAL
N O(OFF) NO(MOV) Output Noise (OFF) Output Noise (Movie) BW = 20Hz to 20KHz Rout and Lout measurement Mode =Movie , BW = 20Hz to 20KHz Rout and Lout measurement Mode = Music , BW = 20Hz to 20KHz, Rout and Lout measurement Mode = Simulated, BW = 20Hz to 20KHz Rout and Lout measurement Av = 0 ; Vin = 1Vrms 8 30 Vrms Vrms Vrms Vrms
N O(MUS)
Output Noise (Music)
30
NO(MON)
Output Noise (Simulated)
30
d SC
Distorsion Channel Separation
0.02 70
0.1
% dB
BUS INPUTS
VIL VIH IIN VO
Note: (1) Bass and Treble response: The center frequency and the resonance quality can be choosen by the external circuitry. A standard first order bass response can be realized by a standard feedback network. (2) The peak voltage of the two input signals must be less then (Lin + Rin)
peak
Input Low Voltage Input High Voltage Input Current Output Voltage SDA Acknowledge IO = 1.6mA 3 -5 0.4
1 +5 0.8
V V A V
VS : 2
* AVin <
VS 2
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TDA7346
I2C BUS INTERFACE Data transmission from microprocessor to the TDA7346 and viceversa takes place through the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected). Data Validity As shown in fig. 3, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. Start and Stop Conditions As shown in fig.4 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. Byte Format Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acFigure 3: Data Validity on the I2CBUS knowledge bit. The MSB is transferred first. Acknowledge The master (P) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 5). The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. The audioprocessor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. Transmission without Acknowledge Avoiding to detect the acknowledge of the audioprocessor, the P can use a simpler transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking and decreases the noise immunity.
Figure 4: Timing Diagram of I2CBUS
Figure 5: Acknowledge on the I2CBUS
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TDA7346
SOFTWARE SPECIFICATION Interface Protocol The interface protocol comprises: A start condition (s) A chip address byte, containing the TDA7346 address (the 8th bit of the byte must be 0). The TDA7346 must always acknowledge at the end of each transmitted byte. A sequence of data (N bytes + achnowledge). A stop condition (P)
TDA7346 ADDRESS
MSB S 1 1
first byte 0 1 1 1 A
LSB 0 ACK
MSB DATA
LSB
ACK
MSB DATA
LSB
ACK P
Data Transferred (N-bytes + Acknowledge) ACK = Acknowledge S = Start P = Stop MAX CLOCK SPEED 100kbits/s
SOFTWARE SPECIFICATION Chip address
1 MSB 1 0 1 1 1 A 0 LSB
A 0 1
CHIP ADDRESS DC (HEX) DE (HEX)
A = Logic level on pin ADDR
A = 1 if ADDR pin = open A = 0 if ADDR pin = connected to ground Software Specification
MSB 0 0 1 1 1 1 1 1 1 1 1 1 0 1 M1 0 0 1 1 M1 M1 M1 M1 M1 A5 A5 M0 0 1 0 1 M0 M0 M0 M0 M0 1 1 0 0 0 0 1 B3 0 0 1 1 1 B2 0 1 0 1 1 B1 C1 C1 D1 E1 1 B0 C0 C0 D0 E0 A4 A4 A3 A3 A2 A2 A1 A1 LSB A0 A0 SUBADDRESS INPUT ATTENUATION R INPUT ATTENUATION L SURROUND MODES SIMULATED MODE MUSIC MODE MOVIE MODE OFF MODE EFFECT CONTROL PHASE SHIFTER 4 CONTROL PHASE SHIFTER 3 CONTROL PHASE SHIFTER 2 CONTROL PHASE SHIFTER 1 CONTROL
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TDA7346
INPUT ATTENUATION MSB I 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 A5 A4 A3 A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 LSB A0 0 1 0 1 0 1 0 1 0.3125 dB STEPS 0 -0.3125 -0.625 -0.9375 -1.25 -1.5625 -1.875 -2.1875 2.5 dB STEPS 0 -2.5 -5 -7.5 -10 -12.5 -15 -17.5
I = 0 Attenuation Input R I = 1 Attenuation Input L Example: to program an R input attenuation equal to -11.25 you have to send 00100100
EFFECT CONTROL (-6 / -21dB) MSB 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M0 M0 M0 M0 M0 M0 M0 M0 M0 M0 M0 M0 M0 M0 M0 M0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 LSB B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1dB STEPS -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 -16 -17 -18 -19 -20 -21
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TDA7346
PHASE SHIFTER 3, 4 MSB C1 1 1 1 1 M1 M1 M1 M1 M0 M0 M0 M0 0 0 0 0 0 0 0 0 F F F F 0 0 1 1 LSB C0 0 1 0 1 12.060 14.450 18.050 39.100 RESISTOR VALUE (K)
F = 0 Phase Shifter 4 F = 1 Phase Shifter 3
PHASE SHIFTER 2 MSB D1 1 1 1 1 M1 M1 M1 M1 M0 M0 M0 M0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 LSB D0 0 1 0 1 5.640 6.770 8.465 18.300 RESISTOR VALUE (K)
PHASE SHIFTER 1 MSB E1 1 1 1 1 M1 M1 M1 M1 M0 M0 M0 M0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 LSB E0 0 1 0 1 11.745 14.150 17.950 37.625 RESISTOR VALUE (K)
Example: to program MOVIE MODE with EFFECT control = -7dB with PHASE SHIFTER resistor = 11.745K, PHASE SHIFTER 2 resistor = 6.77K, PHASE SHIFTER 3 resistor = 12.06K, PHASE SHIFTER 4 resistor = 18.05K, you have to send in sequence 5 bytes: 11010001 11001100 11001001 11000100 11000010
POWER ON RESET INPUT ATTENUATION EFFECT CONTROL SURROUND MODE PHASE SHIFTER 1 RESISTOR VALUE PHASE SHIFTER 2 RESISTOR VALUE PHASE SHIFTER 3, 4 RESISTOR VALUE -19.375dB -20dB OFF MODE 17.950 K 8.465 K 18.050 K
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TDA7346
PIN: HP1 PIN: HP2
LP1
VS 10K
VS 20A 5.5K
60K GND
D94AU198
HP1
60K 5.5K
D94AU199
HP2
PIN: Lin, Rin
PIN: LOUT, ROUT, REAR
VS 20A
VS 20A 100
100K Vref
D94AU123
D94AU204
PIN: SCL, SDA
PIN: ADDR
VS
20A
100K 20A
D94AU205
D94AU212
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TDA7346
PIN: LP
VS
VS
PIN: PS3, PS2
20A
20A
10K
PS3A PS4A
18.050K
D94AU124
D94AU206
PIN: CREF
PIN: PS2
VS
VS 20K 20A
20A
8.465K
20K
D94AU208
PS2A
D94AU125
PIN: PS1
PIN: LP1
VS 20A
VS 20A
17.95K
10K
PS1A
HP1
D94AU126
D94AU211
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TDA7346
SO20 PACKAGE MECHANICAL DATA
DIM. MIN. A a1 a2 b b1 C c1 D E e e3 F L M S 7.4 0.5 12.6 10 1.27 11.43 7.6 1.27 0.75 8 (max.) 0.291 0.020 13.0 10.65 0.35 0.23 0.5 45 (typ.) 0.496 0.394 0.050 0.450 0.299 0.050 0.030 0.512 0.419 0.1 mm TYP. MAX. 2.65 0.3 2.45 0.49 0.32 0.014 0.009 0.020 0.004 MIN. inch TYP. MAX. 0.104 0.012 0.096 0.019 0.013
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TDA7346
DIP20 PACKAGE MECHANICAL DATA
DIM. MIN. a1 B b b1 D E e e3 F I L Z 3.3 1.34 8.5 2.54 22.86 7.1 3.93 0.130 0.053 0.254 1.39 0.45 0.25 25.4 0.335 0.100 0.900 0.280 0.155 1.65 mm TYP. MAX. MIN. 0.010 0.055 0.018 0.010 1.000 0.065 inch TYP. MAX.
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TDA7346
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGSTHOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1997 SGS-THOMSON Microelectronics - Printed in Italy - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
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